stm32l4xx_ll_spi.c 11 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_ll_spi.c
  4. * @author MCD Application Team
  5. * @brief SPI LL module driver.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2017 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. #if defined(USE_FULL_LL_DRIVER)
  19. /* Includes ------------------------------------------------------------------*/
  20. #include "stm32l4xx_ll_spi.h"
  21. #include "stm32l4xx_ll_bus.h"
  22. #ifdef USE_FULL_ASSERT
  23. #include "stm32_assert.h"
  24. #else
  25. #define assert_param(expr) ((void)0U)
  26. #endif /* USE_FULL_ASSERT */
  27. /** @addtogroup STM32L4xx_LL_Driver
  28. * @{
  29. */
  30. #if defined (SPI1) || defined (SPI2) || defined (SPI3)
  31. /** @addtogroup SPI_LL
  32. * @{
  33. */
  34. /* Private types -------------------------------------------------------------*/
  35. /* Private variables ---------------------------------------------------------*/
  36. /* Private constants ---------------------------------------------------------*/
  37. /** @defgroup SPI_LL_Private_Constants SPI Private Constants
  38. * @{
  39. */
  40. /* SPI registers Masks */
  41. #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
  42. SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
  43. SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
  44. SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
  45. SPI_CR1_BIDIMODE)
  46. /**
  47. * @}
  48. */
  49. /* Private macros ------------------------------------------------------------*/
  50. /** @defgroup SPI_LL_Private_Macros SPI Private Macros
  51. * @{
  52. */
  53. #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
  54. || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
  55. || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
  56. || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
  57. #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
  58. || ((__VALUE__) == LL_SPI_MODE_SLAVE))
  59. #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
  60. || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
  61. || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
  62. || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
  63. || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
  64. || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
  65. || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
  66. || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
  67. || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
  68. || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
  69. || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
  70. || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
  71. || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
  72. #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
  73. || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
  74. #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
  75. || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
  76. #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
  77. || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
  78. || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
  79. #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
  80. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
  81. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
  82. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
  83. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
  84. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
  85. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
  86. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
  87. #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
  88. || ((__VALUE__) == LL_SPI_MSB_FIRST))
  89. #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
  90. || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
  91. #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
  92. /**
  93. * @}
  94. */
  95. /* Private function prototypes -----------------------------------------------*/
  96. /* Exported functions --------------------------------------------------------*/
  97. /** @addtogroup SPI_LL_Exported_Functions
  98. * @{
  99. */
  100. /** @addtogroup SPI_LL_EF_Init
  101. * @{
  102. */
  103. /**
  104. * @brief De-initialize the SPI registers to their default reset values.
  105. * @param SPIx SPI Instance
  106. * @retval An ErrorStatus enumeration value:
  107. * - SUCCESS: SPI registers are de-initialized
  108. * - ERROR: SPI registers are not de-initialized
  109. */
  110. ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
  111. {
  112. ErrorStatus status = ERROR;
  113. /* Check the parameters */
  114. assert_param(IS_SPI_ALL_INSTANCE(SPIx));
  115. #if defined(SPI1)
  116. if (SPIx == SPI1)
  117. {
  118. /* Force reset of SPI clock */
  119. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
  120. /* Release reset of SPI clock */
  121. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
  122. status = SUCCESS;
  123. }
  124. #endif /* SPI1 */
  125. #if defined(SPI2)
  126. if (SPIx == SPI2)
  127. {
  128. /* Force reset of SPI clock */
  129. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
  130. /* Release reset of SPI clock */
  131. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
  132. status = SUCCESS;
  133. }
  134. #endif /* SPI2 */
  135. #if defined(SPI3)
  136. if (SPIx == SPI3)
  137. {
  138. /* Force reset of SPI clock */
  139. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
  140. /* Release reset of SPI clock */
  141. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
  142. status = SUCCESS;
  143. }
  144. #endif /* SPI3 */
  145. return status;
  146. }
  147. /**
  148. * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
  149. * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
  150. * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
  151. * @param SPIx SPI Instance
  152. * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
  153. * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
  154. */
  155. ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
  156. {
  157. ErrorStatus status = ERROR;
  158. /* Check the SPI Instance SPIx*/
  159. assert_param(IS_SPI_ALL_INSTANCE(SPIx));
  160. /* Check the SPI parameters from SPI_InitStruct*/
  161. assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
  162. assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
  163. assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
  164. assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
  165. assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
  166. assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
  167. assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
  168. assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
  169. assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
  170. if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
  171. {
  172. /*---------------------------- SPIx CR1 Configuration ------------------------
  173. * Configure SPIx CR1 with parameters:
  174. * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
  175. * - Master/Slave Mode: SPI_CR1_MSTR bit
  176. * - ClockPolarity: SPI_CR1_CPOL bit
  177. * - ClockPhase: SPI_CR1_CPHA bit
  178. * - NSS management: SPI_CR1_SSM bit
  179. * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
  180. * - BitOrder: SPI_CR1_LSBFIRST bit
  181. * - CRCCalculation: SPI_CR1_CRCEN bit
  182. */
  183. MODIFY_REG(SPIx->CR1,
  184. SPI_CR1_CLEAR_MASK,
  185. SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
  186. SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
  187. SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
  188. SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
  189. /*---------------------------- SPIx CR2 Configuration ------------------------
  190. * Configure SPIx CR2 with parameters:
  191. * - DataWidth: DS[3:0] bits
  192. * - NSS management: SSOE bit
  193. */
  194. MODIFY_REG(SPIx->CR2,
  195. SPI_CR2_DS | SPI_CR2_SSOE,
  196. SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
  197. /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
  198. if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
  199. {
  200. LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
  201. }
  202. /*---------------------------- SPIx CRCPR Configuration ----------------------
  203. * Configure SPIx CRCPR with parameters:
  204. * - CRCPoly: CRCPOLY[15:0] bits
  205. */
  206. if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
  207. {
  208. assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
  209. LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
  210. }
  211. status = SUCCESS;
  212. }
  213. return status;
  214. }
  215. /**
  216. * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
  217. * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
  218. * whose fields will be set to default values.
  219. * @retval None
  220. */
  221. void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
  222. {
  223. /* Set SPI_InitStruct fields to default values */
  224. SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
  225. SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
  226. SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
  227. SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
  228. SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
  229. SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
  230. SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
  231. SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
  232. SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
  233. SPI_InitStruct->CRCPoly = 7U;
  234. }
  235. /**
  236. * @}
  237. */
  238. /**
  239. * @}
  240. */
  241. /**
  242. * @}
  243. */
  244. #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
  245. /**
  246. * @}
  247. */
  248. #endif /* USE_FULL_LL_DRIVER */