stm32l4xx_hal_pcd.h 38 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_hal_pcd.h
  4. * @author MCD Application Team
  5. * @brief Header file of PCD HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2017 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. /* Define to prevent recursive inclusion -------------------------------------*/
  19. #ifndef STM32L4xx_HAL_PCD_H
  20. #define STM32L4xx_HAL_PCD_H
  21. #ifdef __cplusplus
  22. extern "C" {
  23. #endif
  24. /* Includes ------------------------------------------------------------------*/
  25. #include "stm32l4xx_ll_usb.h"
  26. #if defined (USB) || defined (USB_OTG_FS)
  27. /** @addtogroup STM32L4xx_HAL_Driver
  28. * @{
  29. */
  30. /** @addtogroup PCD
  31. * @{
  32. */
  33. /* Exported types ------------------------------------------------------------*/
  34. /** @defgroup PCD_Exported_Types PCD Exported Types
  35. * @{
  36. */
  37. /**
  38. * @brief PCD State structure definition
  39. */
  40. typedef enum
  41. {
  42. HAL_PCD_STATE_RESET = 0x00,
  43. HAL_PCD_STATE_READY = 0x01,
  44. HAL_PCD_STATE_ERROR = 0x02,
  45. HAL_PCD_STATE_BUSY = 0x03,
  46. HAL_PCD_STATE_TIMEOUT = 0x04
  47. } PCD_StateTypeDef;
  48. /* Device LPM suspend state */
  49. typedef enum
  50. {
  51. LPM_L0 = 0x00, /* on */
  52. LPM_L1 = 0x01, /* LPM L1 sleep */
  53. LPM_L2 = 0x02, /* suspend */
  54. LPM_L3 = 0x03, /* off */
  55. } PCD_LPM_StateTypeDef;
  56. typedef enum
  57. {
  58. PCD_LPM_L0_ACTIVE = 0x00, /* on */
  59. PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
  60. } PCD_LPM_MsgTypeDef;
  61. typedef enum
  62. {
  63. PCD_BCD_ERROR = 0xFF,
  64. PCD_BCD_CONTACT_DETECTION = 0xFE,
  65. PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
  66. PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
  67. PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
  68. PCD_BCD_DISCOVERY_COMPLETED = 0x00,
  69. } PCD_BCD_MsgTypeDef;
  70. #if defined (USB)
  71. #endif /* defined (USB) */
  72. #if defined (USB_OTG_FS)
  73. typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
  74. typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
  75. typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
  76. #endif /* defined (USB_OTG_FS) */
  77. #if defined (USB)
  78. typedef USB_TypeDef PCD_TypeDef;
  79. typedef USB_CfgTypeDef PCD_InitTypeDef;
  80. typedef USB_EPTypeDef PCD_EPTypeDef;
  81. #endif /* defined (USB) */
  82. /**
  83. * @brief PCD Handle Structure definition
  84. */
  85. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  86. typedef struct __PCD_HandleTypeDef
  87. #else
  88. typedef struct
  89. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  90. {
  91. PCD_TypeDef *Instance; /*!< Register base address */
  92. PCD_InitTypeDef Init; /*!< PCD required parameters */
  93. __IO uint8_t USB_Address; /*!< USB Address */
  94. #if defined (USB_OTG_FS)
  95. PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
  96. PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
  97. #endif /* defined (USB_OTG_FS) */
  98. #if defined (USB)
  99. PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
  100. PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
  101. #endif /* defined (USB) */
  102. HAL_LockTypeDef Lock; /*!< PCD peripheral status */
  103. __IO PCD_StateTypeDef State; /*!< PCD communication state */
  104. __IO uint32_t ErrorCode; /*!< PCD Error code */
  105. uint32_t Setup[12]; /*!< Setup packet buffer */
  106. PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
  107. uint32_t BESL;
  108. uint32_t FrameNumber; /*!< Store Current Frame number */
  109. uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
  110. This parameter can be set to ENABLE or DISABLE */
  111. uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
  112. This parameter can be set to ENABLE or DISABLE */
  113. void *pData; /*!< Pointer to upper stack Handler */
  114. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  115. void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
  116. void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
  117. void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
  118. void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
  119. void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
  120. void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
  121. void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
  122. void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
  123. void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
  124. void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
  125. void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
  126. void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
  127. void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
  128. void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
  129. void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
  130. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  131. } PCD_HandleTypeDef;
  132. /**
  133. * @}
  134. */
  135. /* Include PCD HAL Extended module */
  136. #include "stm32l4xx_hal_pcd_ex.h"
  137. /* Exported constants --------------------------------------------------------*/
  138. /** @defgroup PCD_Exported_Constants PCD Exported Constants
  139. * @{
  140. */
  141. /** @defgroup PCD_Speed PCD Speed
  142. * @{
  143. */
  144. #define PCD_SPEED_FULL USBD_FS_SPEED
  145. /**
  146. * @}
  147. */
  148. /** @defgroup PCD_PHY_Module PCD PHY Module
  149. * @{
  150. */
  151. #define PCD_PHY_ULPI 1U
  152. #define PCD_PHY_EMBEDDED 2U
  153. #define PCD_PHY_UTMI 3U
  154. /**
  155. * @}
  156. */
  157. /** @defgroup PCD_Error_Code_definition PCD Error Code definition
  158. * @brief PCD Error Code definition
  159. * @{
  160. */
  161. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  162. #define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
  163. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  164. /**
  165. * @}
  166. */
  167. /**
  168. * @}
  169. */
  170. /* Exported macros -----------------------------------------------------------*/
  171. /** @defgroup PCD_Exported_Macros PCD Exported Macros
  172. * @brief macros to handle interrupts and specific clock configurations
  173. * @{
  174. */
  175. #if defined (USB_OTG_FS)
  176. #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
  177. #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
  178. #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
  179. ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
  180. #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
  181. #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
  182. #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
  183. *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
  184. #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
  185. *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
  186. #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
  187. ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
  188. #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
  189. #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
  190. #endif /* defined (USB_OTG_FS) */
  191. #if defined (USB)
  192. #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
  193. #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
  194. #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
  195. & (__INTERRUPT__)) == (__INTERRUPT__))
  196. #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
  197. &= (uint16_t)(~(__INTERRUPT__)))
  198. #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
  199. #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
  200. #endif /* defined (USB) */
  201. /**
  202. * @}
  203. */
  204. /* Exported functions --------------------------------------------------------*/
  205. /** @addtogroup PCD_Exported_Functions PCD Exported Functions
  206. * @{
  207. */
  208. /* Initialization/de-initialization functions ********************************/
  209. /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
  210. * @{
  211. */
  212. HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
  213. HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
  214. void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
  215. void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
  216. #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  217. /** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
  218. * @brief HAL USB OTG PCD Callback ID enumeration definition
  219. * @{
  220. */
  221. typedef enum
  222. {
  223. HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
  224. HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
  225. HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
  226. HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
  227. HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
  228. HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
  229. HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
  230. HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
  231. HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
  232. } HAL_PCD_CallbackIDTypeDef;
  233. /**
  234. * @}
  235. */
  236. /** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
  237. * @brief HAL USB OTG PCD Callback pointer definition
  238. * @{
  239. */
  240. typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
  241. typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
  242. typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
  243. typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
  244. typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
  245. typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
  246. typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
  247. /**
  248. * @}
  249. */
  250. HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
  251. pPCD_CallbackTypeDef pCallback);
  252. HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
  253. HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
  254. pPCD_DataOutStageCallbackTypeDef pCallback);
  255. HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
  256. HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
  257. pPCD_DataInStageCallbackTypeDef pCallback);
  258. HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
  259. HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
  260. pPCD_IsoOutIncpltCallbackTypeDef pCallback);
  261. HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
  262. HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
  263. pPCD_IsoInIncpltCallbackTypeDef pCallback);
  264. HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
  265. HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
  266. HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
  267. HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
  268. HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
  269. #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  270. /**
  271. * @}
  272. */
  273. /* I/O operation functions ***************************************************/
  274. /* Non-Blocking mode: Interrupt */
  275. /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
  276. * @{
  277. */
  278. HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
  279. HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
  280. void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
  281. void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
  282. void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
  283. void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
  284. void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
  285. void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
  286. void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
  287. void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
  288. void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  289. void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  290. void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  291. void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
  292. /**
  293. * @}
  294. */
  295. /* Peripheral Control functions **********************************************/
  296. /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
  297. * @{
  298. */
  299. HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
  300. HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
  301. HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
  302. HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
  303. HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  304. HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
  305. HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
  306. HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  307. HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  308. HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  309. HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  310. HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
  311. HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
  312. uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
  313. /**
  314. * @}
  315. */
  316. /* Peripheral State functions ************************************************/
  317. /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
  318. * @{
  319. */
  320. PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
  321. /**
  322. * @}
  323. */
  324. /**
  325. * @}
  326. */
  327. /* Private constants ---------------------------------------------------------*/
  328. /** @defgroup PCD_Private_Constants PCD Private Constants
  329. * @{
  330. */
  331. /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
  332. * @{
  333. */
  334. #if defined (USB_OTG_FS)
  335. #define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */
  336. #endif /* defined (USB_OTG_FS) */
  337. #if defined (USB)
  338. #define USB_WAKEUP_EXTI_LINE (0x1U << 17) /*!< USB FS EXTI Line WakeUp Interrupt */
  339. #endif /* defined (USB) */
  340. /**
  341. * @}
  342. */
  343. #if defined (USB)
  344. /** @defgroup PCD_EP0_MPS PCD EP0 MPS
  345. * @{
  346. */
  347. #define PCD_EP0MPS_64 EP_MPS_64
  348. #define PCD_EP0MPS_32 EP_MPS_32
  349. #define PCD_EP0MPS_16 EP_MPS_16
  350. #define PCD_EP0MPS_08 EP_MPS_8
  351. /**
  352. * @}
  353. */
  354. /** @defgroup PCD_ENDP PCD ENDP
  355. * @{
  356. */
  357. #define PCD_ENDP0 0U
  358. #define PCD_ENDP1 1U
  359. #define PCD_ENDP2 2U
  360. #define PCD_ENDP3 3U
  361. #define PCD_ENDP4 4U
  362. #define PCD_ENDP5 5U
  363. #define PCD_ENDP6 6U
  364. #define PCD_ENDP7 7U
  365. /**
  366. * @}
  367. */
  368. /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
  369. * @{
  370. */
  371. #define PCD_SNG_BUF 0U
  372. #define PCD_DBL_BUF 1U
  373. /**
  374. * @}
  375. */
  376. #endif /* defined (USB) */
  377. /**
  378. * @}
  379. */
  380. #if defined (USB_OTG_FS)
  381. #ifndef USB_OTG_DOEPINT_OTEPSPR
  382. #define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
  383. #endif /* defined USB_OTG_DOEPINT_OTEPSPR */
  384. #ifndef USB_OTG_DOEPMSK_OTEPSPRM
  385. #define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
  386. #endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
  387. #ifndef USB_OTG_DOEPINT_NAK
  388. #define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
  389. #endif /* defined USB_OTG_DOEPINT_NAK */
  390. #ifndef USB_OTG_DOEPMSK_NAKM
  391. #define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
  392. #endif /* defined USB_OTG_DOEPMSK_NAKM */
  393. #ifndef USB_OTG_DOEPINT_STPKTRX
  394. #define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
  395. #endif /* defined USB_OTG_DOEPINT_STPKTRX */
  396. #ifndef USB_OTG_DOEPMSK_NYETM
  397. #define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
  398. #endif /* defined USB_OTG_DOEPMSK_NYETM */
  399. #endif /* defined (USB_OTG_FS) */
  400. /* Private macros ------------------------------------------------------------*/
  401. /** @defgroup PCD_Private_Macros PCD Private Macros
  402. * @{
  403. */
  404. #if defined (USB)
  405. /******************** Bit definition for USB_COUNTn_RX register *************/
  406. #define USB_CNTRX_NBLK_MSK (0x1FU << 10)
  407. #define USB_CNTRX_BLSIZE (0x1U << 15)
  408. /* SetENDPOINT */
  409. #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
  410. (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
  411. /* GetENDPOINT */
  412. #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
  413. /* ENDPOINT transfer */
  414. #define USB_EP0StartXfer USB_EPStartXfer
  415. /**
  416. * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
  417. * @param USBx USB peripheral instance register address.
  418. * @param bEpNum Endpoint Number.
  419. * @param wType Endpoint Type.
  420. * @retval None
  421. */
  422. #define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
  423. (PCD_SET_ENDPOINT((USBx), (bEpNum), \
  424. ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
  425. /**
  426. * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
  427. * @param USBx USB peripheral instance register address.
  428. * @param bEpNum Endpoint Number.
  429. * @retval Endpoint Type
  430. */
  431. #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
  432. /**
  433. * @brief free buffer used from the application realizing it to the line
  434. * toggles bit SW_BUF in the double buffered endpoint register
  435. * @param USBx USB device.
  436. * @param bEpNum, bDir
  437. * @retval None
  438. */
  439. #define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
  440. do { \
  441. if ((bDir) == 0U) \
  442. { \
  443. /* OUT double buffered endpoint */ \
  444. PCD_TX_DTOG((USBx), (bEpNum)); \
  445. } \
  446. else if ((bDir) == 1U) \
  447. { \
  448. /* IN double buffered endpoint */ \
  449. PCD_RX_DTOG((USBx), (bEpNum)); \
  450. } \
  451. } while(0)
  452. /**
  453. * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
  454. * @param USBx USB peripheral instance register address.
  455. * @param bEpNum Endpoint Number.
  456. * @param wState new state
  457. * @retval None
  458. */
  459. #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
  460. do { \
  461. uint16_t _wRegVal; \
  462. \
  463. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
  464. /* toggle first bit ? */ \
  465. if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
  466. { \
  467. _wRegVal ^= USB_EPTX_DTOG1; \
  468. } \
  469. /* toggle second bit ? */ \
  470. if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
  471. { \
  472. _wRegVal ^= USB_EPTX_DTOG2; \
  473. } \
  474. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  475. } while(0) /* PCD_SET_EP_TX_STATUS */
  476. /**
  477. * @brief sets the status for rx transfer (bits STAT_TX[1:0])
  478. * @param USBx USB peripheral instance register address.
  479. * @param bEpNum Endpoint Number.
  480. * @param wState new state
  481. * @retval None
  482. */
  483. #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
  484. do { \
  485. uint16_t _wRegVal; \
  486. \
  487. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
  488. /* toggle first bit ? */ \
  489. if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
  490. { \
  491. _wRegVal ^= USB_EPRX_DTOG1; \
  492. } \
  493. /* toggle second bit ? */ \
  494. if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
  495. { \
  496. _wRegVal ^= USB_EPRX_DTOG2; \
  497. } \
  498. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  499. } while(0) /* PCD_SET_EP_RX_STATUS */
  500. /**
  501. * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
  502. * @param USBx USB peripheral instance register address.
  503. * @param bEpNum Endpoint Number.
  504. * @param wStaterx new state.
  505. * @param wStatetx new state.
  506. * @retval None
  507. */
  508. #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
  509. do { \
  510. uint16_t _wRegVal; \
  511. \
  512. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
  513. /* toggle first bit ? */ \
  514. if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
  515. { \
  516. _wRegVal ^= USB_EPRX_DTOG1; \
  517. } \
  518. /* toggle second bit ? */ \
  519. if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
  520. { \
  521. _wRegVal ^= USB_EPRX_DTOG2; \
  522. } \
  523. /* toggle first bit ? */ \
  524. if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
  525. { \
  526. _wRegVal ^= USB_EPTX_DTOG1; \
  527. } \
  528. /* toggle second bit ? */ \
  529. if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
  530. { \
  531. _wRegVal ^= USB_EPTX_DTOG2; \
  532. } \
  533. \
  534. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  535. } while(0) /* PCD_SET_EP_TXRX_STATUS */
  536. /**
  537. * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
  538. * /STAT_RX[1:0])
  539. * @param USBx USB peripheral instance register address.
  540. * @param bEpNum Endpoint Number.
  541. * @retval status
  542. */
  543. #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
  544. #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
  545. /**
  546. * @brief sets directly the VALID tx/rx-status into the endpoint register
  547. * @param USBx USB peripheral instance register address.
  548. * @param bEpNum Endpoint Number.
  549. * @retval None
  550. */
  551. #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
  552. #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
  553. /**
  554. * @brief checks stall condition in an endpoint.
  555. * @param USBx USB peripheral instance register address.
  556. * @param bEpNum Endpoint Number.
  557. * @retval TRUE = endpoint in stall condition.
  558. */
  559. #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
  560. #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
  561. /**
  562. * @brief set & clear EP_KIND bit.
  563. * @param USBx USB peripheral instance register address.
  564. * @param bEpNum Endpoint Number.
  565. * @retval None
  566. */
  567. #define PCD_SET_EP_KIND(USBx, bEpNum) \
  568. do { \
  569. uint16_t _wRegVal; \
  570. \
  571. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
  572. \
  573. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
  574. } while(0) /* PCD_SET_EP_KIND */
  575. #define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
  576. do { \
  577. uint16_t _wRegVal; \
  578. \
  579. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
  580. \
  581. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  582. } while(0) /* PCD_CLEAR_EP_KIND */
  583. /**
  584. * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
  585. * @param USBx USB peripheral instance register address.
  586. * @param bEpNum Endpoint Number.
  587. * @retval None
  588. */
  589. #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
  590. #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
  591. /**
  592. * @brief Sets/clears directly EP_KIND bit in the endpoint register.
  593. * @param USBx USB peripheral instance register address.
  594. * @param bEpNum Endpoint Number.
  595. * @retval None
  596. */
  597. #define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
  598. #define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
  599. /**
  600. * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
  601. * @param USBx USB peripheral instance register address.
  602. * @param bEpNum Endpoint Number.
  603. * @retval None
  604. */
  605. #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
  606. do { \
  607. uint16_t _wRegVal; \
  608. \
  609. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
  610. \
  611. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
  612. } while(0) /* PCD_CLEAR_RX_EP_CTR */
  613. #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
  614. do { \
  615. uint16_t _wRegVal; \
  616. \
  617. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
  618. \
  619. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
  620. } while(0) /* PCD_CLEAR_TX_EP_CTR */
  621. /**
  622. * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
  623. * @param USBx USB peripheral instance register address.
  624. * @param bEpNum Endpoint Number.
  625. * @retval None
  626. */
  627. #define PCD_RX_DTOG(USBx, bEpNum) \
  628. do { \
  629. uint16_t _wEPVal; \
  630. \
  631. _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
  632. \
  633. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
  634. } while(0) /* PCD_RX_DTOG */
  635. #define PCD_TX_DTOG(USBx, bEpNum) \
  636. do { \
  637. uint16_t _wEPVal; \
  638. \
  639. _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
  640. \
  641. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
  642. } while(0) /* PCD_TX_DTOG */
  643. /**
  644. * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
  645. * @param USBx USB peripheral instance register address.
  646. * @param bEpNum Endpoint Number.
  647. * @retval None
  648. */
  649. #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
  650. do { \
  651. uint16_t _wRegVal; \
  652. \
  653. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
  654. \
  655. if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
  656. { \
  657. PCD_RX_DTOG((USBx), (bEpNum)); \
  658. } \
  659. } while(0) /* PCD_CLEAR_RX_DTOG */
  660. #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
  661. do { \
  662. uint16_t _wRegVal; \
  663. \
  664. _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
  665. \
  666. if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
  667. { \
  668. PCD_TX_DTOG((USBx), (bEpNum)); \
  669. } \
  670. } while(0) /* PCD_CLEAR_TX_DTOG */
  671. /**
  672. * @brief Sets address in an endpoint register.
  673. * @param USBx USB peripheral instance register address.
  674. * @param bEpNum Endpoint Number.
  675. * @param bAddr Address.
  676. * @retval None
  677. */
  678. #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
  679. do { \
  680. uint16_t _wRegVal; \
  681. \
  682. _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
  683. \
  684. PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
  685. } while(0) /* PCD_SET_EP_ADDRESS */
  686. /**
  687. * @brief Gets address in an endpoint register.
  688. * @param USBx USB peripheral instance register address.
  689. * @param bEpNum Endpoint Number.
  690. * @retval None
  691. */
  692. #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
  693. #define PCD_EP_TX_CNT(USBx, bEpNum) \
  694. ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
  695. ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
  696. #define PCD_EP_RX_CNT(USBx, bEpNum) \
  697. ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
  698. ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
  699. /**
  700. * @brief sets address of the tx/rx buffer.
  701. * @param USBx USB peripheral instance register address.
  702. * @param bEpNum Endpoint Number.
  703. * @param wAddr address to be set (must be word aligned).
  704. * @retval None
  705. */
  706. #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
  707. do { \
  708. __IO uint16_t *_wRegVal; \
  709. uint32_t _wRegBase = (uint32_t)USBx; \
  710. \
  711. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  712. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
  713. *_wRegVal = ((wAddr) >> 1) << 1; \
  714. } while(0) /* PCD_SET_EP_TX_ADDRESS */
  715. #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
  716. do { \
  717. __IO uint16_t *_wRegVal; \
  718. uint32_t _wRegBase = (uint32_t)USBx; \
  719. \
  720. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  721. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
  722. *_wRegVal = ((wAddr) >> 1) << 1; \
  723. } while(0) /* PCD_SET_EP_RX_ADDRESS */
  724. /**
  725. * @brief Gets address of the tx/rx buffer.
  726. * @param USBx USB peripheral instance register address.
  727. * @param bEpNum Endpoint Number.
  728. * @retval address of the buffer.
  729. */
  730. #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
  731. #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
  732. /**
  733. * @brief Sets counter of rx buffer with no. of blocks.
  734. * @param pdwReg Register pointer
  735. * @param wCount Counter.
  736. * @param wNBlocks no. of Blocks.
  737. * @retval None
  738. */
  739. #define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
  740. do { \
  741. (wNBlocks) = (wCount) >> 5; \
  742. if (((wCount) & 0x1fU) == 0U) \
  743. { \
  744. (wNBlocks)--; \
  745. } \
  746. *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
  747. } while(0) /* PCD_CALC_BLK32 */
  748. #define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
  749. do { \
  750. (wNBlocks) = (wCount) >> 1; \
  751. if (((wCount) & 0x1U) != 0U) \
  752. { \
  753. (wNBlocks)++; \
  754. } \
  755. *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
  756. } while(0) /* PCD_CALC_BLK2 */
  757. #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
  758. do { \
  759. uint32_t wNBlocks; \
  760. \
  761. if ((wCount) > 62U) \
  762. { \
  763. PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
  764. } \
  765. else \
  766. { \
  767. if ((wCount) == 0U) \
  768. { \
  769. *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
  770. *(pdwReg) |= USB_CNTRX_BLSIZE; \
  771. } \
  772. else \
  773. { \
  774. PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
  775. } \
  776. } \
  777. } while(0) /* PCD_SET_EP_CNT_RX_REG */
  778. #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
  779. do { \
  780. uint32_t _wRegBase = (uint32_t)(USBx); \
  781. __IO uint16_t *pdwReg; \
  782. \
  783. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  784. pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
  785. PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
  786. } while(0)
  787. /**
  788. * @brief sets counter for the tx/rx buffer.
  789. * @param USBx USB peripheral instance register address.
  790. * @param bEpNum Endpoint Number.
  791. * @param wCount Counter value.
  792. * @retval None
  793. */
  794. #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
  795. do { \
  796. uint32_t _wRegBase = (uint32_t)(USBx); \
  797. __IO uint16_t *_wRegVal; \
  798. \
  799. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  800. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
  801. *_wRegVal = (uint16_t)(wCount); \
  802. } while(0)
  803. #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
  804. do { \
  805. uint32_t _wRegBase = (uint32_t)(USBx); \
  806. __IO uint16_t *_wRegVal; \
  807. \
  808. _wRegBase += (uint32_t)(USBx)->BTABLE; \
  809. _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
  810. PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
  811. } while(0)
  812. /**
  813. * @brief gets counter of the tx buffer.
  814. * @param USBx USB peripheral instance register address.
  815. * @param bEpNum Endpoint Number.
  816. * @retval Counter value
  817. */
  818. #define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
  819. #define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
  820. /**
  821. * @brief Sets buffer 0/1 address in a double buffer endpoint.
  822. * @param USBx USB peripheral instance register address.
  823. * @param bEpNum Endpoint Number.
  824. * @param wBuf0Addr buffer 0 address.
  825. * @retval Counter value
  826. */
  827. #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
  828. do { \
  829. PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
  830. } while(0) /* PCD_SET_EP_DBUF0_ADDR */
  831. #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
  832. do { \
  833. PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
  834. } while(0) /* PCD_SET_EP_DBUF1_ADDR */
  835. /**
  836. * @brief Sets addresses in a double buffer endpoint.
  837. * @param USBx USB peripheral instance register address.
  838. * @param bEpNum Endpoint Number.
  839. * @param wBuf0Addr: buffer 0 address.
  840. * @param wBuf1Addr = buffer 1 address.
  841. * @retval None
  842. */
  843. #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
  844. do { \
  845. PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
  846. PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
  847. } while(0) /* PCD_SET_EP_DBUF_ADDR */
  848. /**
  849. * @brief Gets buffer 0/1 address of a double buffer endpoint.
  850. * @param USBx USB peripheral instance register address.
  851. * @param bEpNum Endpoint Number.
  852. * @retval None
  853. */
  854. #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
  855. #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
  856. /**
  857. * @brief Gets buffer 0/1 address of a double buffer endpoint.
  858. * @param USBx USB peripheral instance register address.
  859. * @param bEpNum Endpoint Number.
  860. * @param bDir endpoint dir EP_DBUF_OUT = OUT
  861. * EP_DBUF_IN = IN
  862. * @param wCount: Counter value
  863. * @retval None
  864. */
  865. #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
  866. do { \
  867. if ((bDir) == 0U) \
  868. /* OUT endpoint */ \
  869. { \
  870. PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
  871. } \
  872. else \
  873. { \
  874. if ((bDir) == 1U) \
  875. { \
  876. /* IN endpoint */ \
  877. PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
  878. } \
  879. } \
  880. } while(0) /* SetEPDblBuf0Count*/
  881. #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
  882. do { \
  883. uint32_t _wBase = (uint32_t)(USBx); \
  884. __IO uint16_t *_wEPRegVal; \
  885. \
  886. if ((bDir) == 0U) \
  887. { \
  888. /* OUT endpoint */ \
  889. PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
  890. } \
  891. else \
  892. { \
  893. if ((bDir) == 1U) \
  894. { \
  895. /* IN endpoint */ \
  896. _wBase += (uint32_t)(USBx)->BTABLE; \
  897. _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
  898. *_wEPRegVal = (uint16_t)(wCount); \
  899. } \
  900. } \
  901. } while(0) /* SetEPDblBuf1Count */
  902. #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
  903. do { \
  904. PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
  905. PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
  906. } while(0) /* PCD_SET_EP_DBUF_CNT */
  907. /**
  908. * @brief Gets buffer 0/1 rx/tx counter for double buffering.
  909. * @param USBx USB peripheral instance register address.
  910. * @param bEpNum Endpoint Number.
  911. * @retval None
  912. */
  913. #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
  914. #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
  915. #endif /* defined (USB) */
  916. /**
  917. * @}
  918. */
  919. /**
  920. * @}
  921. */
  922. /**
  923. * @}
  924. */
  925. #endif /* defined (USB) || defined (USB_OTG_FS) */
  926. #ifdef __cplusplus
  927. }
  928. #endif
  929. #endif /* STM32L4xx_HAL_PCD_H */